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this product conforms to specific ations per the terms of the ramtron ramtron international corporation standard warranty. the product has completed ramtrons internal 1850 ramtron drive, colorado springs, co 80921 qualification testing and has reached production status. (800) 545 - fram, (7 19) 481 - 7000 http://www.ramtron.com rev. 3.0 august 2012 page 1 of 17 fm 25v20 2m b serial 3v f - ram memor y features 2m bi t ferroelectric nonvolatile ram ? organized as 256k x 8 bits ? high endurance 100 trillion (10 14 ) read/writes ? 10 year data retention ? nodelay? writes ? advanced high - reliability ferroelectric process very fast serial peripheral interface - spi ? up to 40 mhz frequency ? direct hardware replacement for serial flash ? spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) write protection scheme ? hardware protection ? software protection device id ? device id reads out manufacturer id & part id low voltage, low power ? low voltage oper ation 2.0 v C 3.6v ? 10 0 ? a standby current (typ.) ? 3 ? a sleep mode current (typ.) industry standard configurations ? industrial temperature - 40 ? c to +85 ? c ? 8 - pin green/rohs eiaj soic package ? 8 - pin green/roh s tdfn package ? 8 - pin green/pohs pdip package description the fm 25v20 is a 2 - m egabit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f - ram is nonvolatile and performs reads and writes like a ram . it provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash and other nonvolatile memories. unlike serial flash , the fm 25v20 performs write operations at bu s speed. no write delays are incurred. data is written to the memory array immediately after it has been transferred to the devic e. the next bu s cycle may commence without the need for data polling . t he product offers very high write endurance , orders of m agnitude more endurance than serial flash. also, f - ram exhibits low er power consumption than serial flash . these capabilities make the fm 25v20 ideal for nonvolatile memory applications requiring frequent or rapid writes or low power operation. examples r ange from data collection, where the number of write cycle s may be critical, to demanding controls whe re the long write time of serial flash can cause data loss. the fm 25v20 provides substantial be nefits to users of serial flash as a hardware drop - in rep lacement. the device use s the high - speed spi bus, which enhances the high - speed write capability of f - ram technology. the device incorporate s a read - only device id that allows the host to determine the manufacturer, product density, a nd product revision. t he device is guaranteed over an industrial temperature range of - 40c to +85c. pin configuration pin name function /s chip select /w write protect /hold hold c serial clock d serial da ta input q serial data output vdd supply voltage vss ground /s q /w vss vdd /hold c d 1 2 3 4 8 7 6 5 top view s q w vss vdd hold c d 1 2 3 4 8 7 6 5
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 2 of 17 figure 1. block diagram pin descriptions pin name i/o description / s input chip select: this active - low input activates the device. when high, the device e nters low - power standby mode, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the c signal. a falling edge on / s must occur prior to every op - code. c input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 40 mhz and may be interrupted at any time. /hold input hold: the /hold pin is us ed when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on c or / s . all transitions on /hold must occur while c is low. i f it is not used, the /hold p in should be tied to v dd . /w input write protect: this active - low pin prevents write operations to the status register only. a complete explanation of write protection is provided on pages 6 and 7. if it is not used, the /w pin should be tied to v dd . d input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of c and is ignored at other times. it should always be driven to a valid logic level to meet i dd specifications. * d may be connected to q for a singl e pin data interface. q output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * q may be connected to d for a single pin data interface. vdd supply power supply vss supply ground instruction decode clock generator control logic write protect instruction register address register counter 32 k x 64 fram array 18 data i / o register 8 nonvolatile status register 3 w s c q d hold
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 3 of 17 overview the fm 25v20 is a serial f - ram memory. the memory array is logically organized as 262,144 x 8 and is accessed using an industry standard serial periphera l interface or spi bus. functional operation of the f - ram is similar to serial flash . the major difference s between the fm 25v20 and a serial flash with the same pinout are the f - ram s superior write performance , very high endurance, and lower power consump tion. memory architecture when accessing the fm 25v20 , the user addresses 256k locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code, and a t hree - byte address. the complete address of 18 - bits specifies each byte address uniquely. most functions of the fm 25v20 either are controlled by the spi interface or are handled automatically by on - board circuitry. the acce ss time for memory operation is essentially zero, beyond the time needed for the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike serial flash , it is not necessary to poll the device for a ready condition since wr ites occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in more detail in the interface section. users expect several obvious system benefits from the fm 25v20 du e to its fast write cycle and high endurance as compared to serial flash . in addition there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less suscepti ble to corruption than serial flash since it is completed quickly. by contrast, serial flash requiring milliseconds to write is vulnerable to noise during much of the cycle. serial peripheral interface C spi bus the fm 25v20 employs a serial peripheral interface (spi) bus. it is speci fied to operate a t speeds up to 40 mhz . this high - speed serial bus provides high performance serial communication to a host microcontroller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordina ry port pins for microcontrollers that do not. the fm 25v20 operates in spi mode 0 and 3. protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device i s activated using a chip select. once chip select is activated by the bus master, the fm 25v20 will begin monitoring the clock and data lines. the relationship between the falling edge of / s , the clock and data is dictated by the spi mode. the device will m ake a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm 25v20 supports only modes 0 and 3. figure 2 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked int o the fm 25v20 on the rising edge of c and data is expected on the first rising edge after / s goes active. if the clock starts from a high state, it will fall prior to the first data transfer in order to create the first rising edge. the spi protocol is c ontrolled by op - codes. these op - codes specify the commands to the device. after / s is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. certain op - codes are comman ds with no subsequent data transfer. the / s must go inactive after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select. spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 2. spi modes 0 & 3 s c d m s b l s b 7 6 5 4 3 2 1 0 s c d m s b l s b 7 6 5 4 3 2 1 0
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 4 of 17 system hookup the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. a typical system configuration uses one or more fm 25v20 devices with a microc ontroller that has a dedicated spi port, as figure 3 illustrates. note that the clock, data - in, and data - out pins are common among all devices. the chip select and hold pins must be driven separately for each fm 25v20 device. for a microcontroller that h as no dedicated spi bus, a general purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins together and tie off the hold pin. figure 4 shows a configuration that uses only three pins. figure 3 . 4 mbit ( 512 kb) system configuration with spi port figure 4 . system configuration without spi port s p i m i c r o c o n t r o l l e r f m 2 5 v 2 0 q d c s h o l d f m 2 5 v 2 0 q d c s h o l d s c k m o s i m i s o s s 1 s s 2 h o l d 1 h o l d 2 m o s i : m a s t e r o u t s l a v e i n m i s o : m a s t e r i n s l a v e o u t s s : s l a v e s e l e c t m i c r o c o n t r o l l e r f m 2 5 v 2 0 q d c s h o l d p 1 . 0 p 1 . 1 p 1 . 2 v d d
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 5 of 17 power up to first access the fm 25v20 is not acc essible for a period of time ( t pu ) after power up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first / s low. data transfer all data transfers to and from the fm 25v20 occur in 8 - bit groups. they are synchronized to the clock signal (c) , and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of c . outputs are driven from the falling edge of clock c . command structure there are nine commands called op - codes that can be issued by the bus master to the fm 25v20 . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function , such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the status register . the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code c ommands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b fstrd fast read memory data 0000 1011b write write memory data 0000 0010b sleep enter sleep mode 1011 1001b rdid read device id 1001 1111b wren C set write enable latch the fm 25v20 will power up with writes disabled. the wren command must be issued prior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include wri ting the status register (wrsr) and w riting the memory (write) . sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register , called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit. completing any write operation will automatically clear the write - enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. figure 5. wren bus configuration wrdi C write disable the wrdi command di sables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 6. wrdi bus configuration rdsr C read status register the rdsr command allows the bus master to verify the contents of the status r egister. reading status provides information about the current state of the write protection features. fol lowing the rdsr op - code, the fm 25v20 will return one byte with the contents of the status r egister. the status r egister i s described in detail in the section below . 0 0 0 0 0 1 1 0 s c d q hi - z 0 1 2 3 4 5 6 7 0 0 0 0 0 1 0 0 s c d q hi - z 0 1 2 3 4 5 6 7
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 6 of 17 wrsr C write status register the wrsr command allows the user to select certain write pro tection features by writing a byte to the status r egister. prior to issuing a wrsr command, the /w pin must be high or inactive. prior to sending the wrsr command, the user must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. the bus configuration of rdsr and wrsr are shown below. figure 7. rdsr bus configuration figure 8. wrsr bus configuration status register & write protection the write protection features of the fm 25v20 are multi - tiered. taking the /w pin to a logic low state is the hardw are write - protect function. status register write operations are blocked when /w is low. to write the memory with /w high, a wren op - code must first be issued. assuming that writes are enabled using wren and by /w , writes to memory are controlled by the status r egister. as described above, writes to the s tatus r egister are performed using the wrsr command and subject to the /w pin. the status r egister is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 1 0 0 bp1 bp0 wel 0 bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1 , and none of these bits can be modified. n ote that bit 0 ( ready in serial flash ) is unnecessary as the f - ram writes in real - time and is never bu sy, so it reads out as a 0. there is an exception to this when the device is waking up from sleep mode, which is described in the sleep mode section . the bp1 and bp0 cont rol software write protection features. they are nonvolatile (shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the s tatus r egister has no effect on its state. this bit is internally se t and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify po rtions of memory that are write - protected as shown in the following table. table 3. block memory write protection bp1 bp0 prot ected address range 0 0 none 0 1 30 000h to 3 f fffh (upper ?) 1 0 2 0 000h to 3 f fffh (upper ?) 1 1 0 0000h to 3 f fffh (all) the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write pro tection features protect inadvertent changes to the block protect bits. the wpen bit controls the effect of the hardware /w pin. when wpen is low, the /w pin is ignored. when wpen is high, the /w pin controls write access to the s tatus r egister. thus the status r egister is write protected if wpen=1 and /w =0. this scheme provides a write protection mechanism, which can prevent software from writing the memory s c d q s c d q
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 7 of 17 under any circumstances. this occurs if the bp1 and bp0 bits are set to 1, the wpen bit is set to 1, and the /w pin is low. this occurs because the block protect bits prevent writing memory and the /w signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a writ e operation. the following table summarizes the write protection conditions. table 4. write protection wel wpen /w protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 pr otected unprotected protected 1 1 1 protected unprotected unprotected memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the f - ram te chnology. unlike serial flash , the fm 2 5v20 can perform sequential write s at bus speed. no page buffer is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - c ode is followed by a three - byte address value , which specifies the 18 - bit address of the first data byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master con tinues to issue clocks. if the last address of 3 ffff h is reached, the counter will roll over to 0 0000h. data is written msb first. a write operation is shown in figure 9. unlike serial flash , any number of bytes can be written sequentially and each byte i s written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of / s terminates a write op - code operation. asserting /w active in the middle of a write operation will have no e ffect until the next falling edge of / s . read o peration after the falling edge of / s , the bus master can issue a read op - code. followin g this instruction is a three - byte address value (a17 - a0), specifying the address of the first data byte of the read operation. after the op - code and address are comple te, the d pin is ignored. the bus master issues 8 clocks, with one bit read out for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 3 ffffh is reached, the counter will roll over to 0 000 0h. data is read msb first. the rising edge of / s terminates a read op - code operation and tri - states the q pin . a read operation is shown in figure 10 . fast read operation the fm 25v20 supports the fast read op - code (0bh) that is found on s erial flash dev ices. it is implemented for code compatibility with serial flash devices . following this instruct ion is a three - byte address (a17 - a0), specifying the address of the first data byte of the read operation. a dummy address byte follows the address. it inserts one byte of read latency. the d pin is ignored after the op - code, three - byte address, and dummy byte are complete. the bus master issues 8 clocks, with one bit read out for each. the fast read operation is otherwise the same as an ordinary read. if the la st address of 3 ffffh is reached, the counter will roll over to 00000h. data is read msb first. the rising edge of /s terminates a fast read op - code operation and tri - states the q pin. a f ast r ead operation is shown in figure 11. hold the fm 25v20 device ha s a /hold pin that can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while c is low, the current operation will pause. taking the /hold pin high while c is low will resume an operation. the transitio ns of /hold must occur while c is low, but the c and / s pins can toggle during a hold state.
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 8 of 17 figure 9. memory write with 3 - byte address figure 10. memory read with 3 - byte address figure 11. fast read with 3 - byte address and dummy byte 7 6 0 1 2 3 4 5 6 7 0 1 2 3 5 4 5 6 7 0 1 2 3 4 5 6 7 op - code 0 0 0 0 1 0 1 m s b 18 - bit address 0 0 0 0 a 1 x x x x 7 6 5 4 3 2 1 0 l sb m s b l s b d a t a 1 a 2 s c d q a 0 dummy byte 7 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 m s b 1 8 - b i t a d d r e s s 0 0 0 0 0 a17 7 6 5 4 3 2 1 0 l s b m s b l s b d a t a 1 0 s c d q a16 a 3 a 1 a 2 a 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 o p - c o d e 0 0 0 0 0 0 1 0 m s b 1 8 - b i t a d d r e s s 0 a17 6 0 0 0 0 0 s c d q 7 a16 a 1 a 2 a 3 4 5 6 7 0 1 2 3 4 5 6 7 a 0 7 6 5 4 3 2 1 0 l s b m s b l s b d a t a
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 9 of 17 sleep mode a low power mode called sleep mode is implemented on the fm 25v20 device . th e device will enter this low power state when the sle ep op - code b9h is clocked - in and a rising edge of / s is applied . once in sleep mode, the c and d pins are ignored and q will be hi gh - z, but the device contin ues to monitor the /s pin. on the next falling edge of /s, the device will return to normal operation within t rec (400 ? s max.). the q pin remains in a hi - z state during the wakeup period. the device will not necessarily respond to an opcode within the wa keup period. to start the wakeup procedure, the controller may send a dummy read, for example, and wait the remaining t rec time. figure 12. sleep mode entry device id the fm 25v20 device can be inter rogated for its manuf acturer, product identification , and die revision . the r did op - code 9fh allows the user to read the manufacturer id and product id, both of which are read - only bytes . the jedec - assigned manufacturer id places the ramtron identifier in bank 7, therefore t here are six bytes of the continuation code 7fh followed by the single byte c2h. there are two bytes of product id, which includes a family code, a density code, a sub code, and product revision code. table 5 . manufacturer and product id bit 7 6 5 4 3 2 1 0 hex manufacturer id 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuation code 0 1 1 1 1 1 1 1 7f continuatio n code 1 1 0 0 0 0 1 0 c2 jedec assigned ramtron c2h in bank 7 family density hex device id (1 st byte) 0 0 1 0 0 1 0 1 2 5 h density: 03h=512k, 04 h =1m , 05 h =2m , 06 h =4m sub rev. rsvd device id (2 nd byte) 0 0 0 0 0 0 0 0 00h 00h=fm 25v 2 0 figure 1 3 . read device id s c d q e nter sleep mode s c d q 7fh 7f h c2 h 00 h six bytes of continuation code 7fh 9f h 25 h 1 6 . . . . . . .
fm25v20 - 2mb spi f - ram rev. 3.0 august 2012 page 10 of 1 7 endurance the fm 25v20 device is capable of being accessed at least 10 14 times , read s or write s . a n f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is appl ied on a row basis for each access (read or write) to the memory array . the f - ram architecture is based on an array of rows and columns. rows are defined by a1 7 - a3 and column addresses by a2 - a0. see block diagram (pg 2) whic h shows the array as 32 k rows of 64 - bits each . t he entire row is internally a ccessed once whether a single byte or all eight bytes are read or written. each byte in t he row is counted only on c e in an endurance calculation . the table below shows endurance calculations for 64 - byte repeating loop, which includes an op - code, a starting address, and a sequential 64 - byte data stream . this causes each byte to experience one endurance cycle through the loop. f - ram read and write endurance is virtually unlimited even at 40 mhz clock rate. table 6 . ti me to reach 100 trillion cycles for repeating 64 - byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach 10 14 cycles 40 73,52 0 2.32 x 10 12 43 .1 10 1 8, 38 0 5. 79 x 10 1 1 172. 7 5 9 , 19 0 2. 90 x 10 1 1 345 .4
fm25v20 - 2mb spi f - ram rev. 3.0 august 2012 page 11 of 1 7 electrical specification s absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to + 4 . 5 v v in voltage on any pin with respect to v ss - 1.0v to + 4.5 v and v in < v dd +1.0v t stg storage temperature - 55 ? c to + 125 ? c t lead lead tempera ture (soldering, 10 seconds) 26 0 ? c v esd electrostatic discharge voltage - human body model ( jede c std jesd22 - a114 - b) - charged device model ( jede c std jesd22 - c101 - a) - machine model (jedec std jesd22 - a115 - a) 4kv 1.25kv 2 5 0v package moisture sen sitivity level msl - 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliabil ity. dc operating conditions ( t a = - 40 ? c to + 85 ? c, v dd = 2.0 v to 3.6v unless otherwise specified) s ymbol parameter min typ max units notes v dd power supply voltage 2.0 3.3 3.6 v i dd power supply operating current @ c = 1 mhz @ c = 40 mhz 0. 1 3 1.4 0.30 3.0 m a ma 1 i sb standby current @ t a = 25 c @ t a = 85 c 100 - 150 250 ? a ? a 2 i zz sleep mode current @ t a = 25 c @ t a = 85 c 3 - 5 8 ? a ? a 3 i li input leakage current - ? 1 ? a 4 i lo output leakage current - ? 1 ? a 4 v ih input high voltage 0.7 v dd v dd + 0.3 v v il input low voltage - 0.3 0.3 v dd v v oh1 output high voltage ( i oh = - 1 ma, v dd =2.7v) 2.4 - v v oh2 output high voltage ( i oh = - 100 ? a) v dd - 0.2 - v v ol1 o utput low voltage ( i ol = 2 ma, v dd =2.7v) - 0.4 v v ol2 output low voltage ( i ol = 150 ? a) - 0.2 v notes 1. c toggling between v dd - 0. 2 v and v ss , other inputs v ss or v dd - 0. 2 v. q=open. 2. / s =v dd . all inputs v ss or v dd . 3. in sleep mode and /s=v dd . all inputs v ss o r v dd . 4. v ss ? v in ? v dd and v ss ? v out ? v dd . data retention ( t a = - 40 ? c to + 85 ? c) symbol parameter min max units notes t dr data retention 10 - years
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 12 of 17 a c parameters ( t a = - 40 ? c to + 85 ? c, c l = 30pf , unless otherwise specified ) v dd 2.0 to 2.7 v v dd 2.7 to 3.6 v symbol parameter min max min max units notes f ck c clock frequency 0 25 0 40 mhz t ch clock high time 20 11 ns 1 t cl clock low time 20 11 ns 1 t csu chip select setup 12 10 ns t csh chip select hold 12 10 ns t od output disable time 20 12 ns 3 t odv output data valid time 18 9 ns t oh output hold time 0 0 ns 3 t d deselect time 60 40 ns t r data in rise time 50 50 ns 2, 4 t f data in fall time 50 50 ns 2, 4 t su data setup time 8 5 ns t h data hold time 8 5 ns t hs /hold setup time 12 10 ns t hh /hold hold time 12 10 ns 3 t hz /hold low to hi - z 25 20 ns 4 t lz /hold high to data active 25 20 ns 4 notes 1. t ch + t cl = 1/f ck . 2. rise and fall times measured between 10% and 90% of waveform. 3. guaranteed by desi gn. 4. guaranteed by design for 1mhz f ck . capacitance ( t a = 25 ? c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output c apacitance ( q ) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. guaranteed by design. ac test conditions input pulse le vels 10% and 90% of v dd input rise and fall times 3 ns input and output timing levels 50% of v dd output load capacitance 30 pf serial data bus timing /hold timing s c d q 1 / t c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 13 of 17 power cycle timing power cycle & sleep timing ( t a = - 40 ? c to + 85 ? c, v dd = 2.0 v to 3.6v , unless otherwise specified ) symbol parameter min max units notes t vr v dd rise time 50 - ? s/v 1 t vf v dd fall time 100 - ? s/v 1 t pu power up (v dd min) to first access (/ s low) 1 - ms t pd last access (/ s high) to power down (v dd min) 0 - ? s 2 t rec recovery time from sleep mode - 4 5 0 ? s notes 1. slope measured at any point on v dd waveform. 2. guaranteed by design . s c q hold t hs t hh t hz t lz t hs t hh v d d m i n . v d d s t v r t p d t p u t v f
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 14 of 17 mechanical drawing 8 - pin tdfn * (5.0 mm x 6.0 mm body, 1.27 mm pad pitch) note: all dimensions in millimeters . this package is footprint compatible with the 8 - pin soic. the exposed pad should be left floating. tdfn package marking scheme for body size 5.0mm x 6.0mm legend: r=ramtron, g=green tdfn package xxxx=base part number , t=temperature (blank=ind., c=comm.) llll= lot code yy=year, ww=work week example: green tdfn package, fm25v20, lot 0012, year 2 010, work we ek 29 rg5v 20 0012 1029 rg xxxx t llll yyww p i n 1 6 . 0 b s c 5 . 0 b s c 0 . 7 5 0 . 0 5 0 . 4 0 0 . 0 5 1 . 2 7 0 . 2 0 r e f . 0 . 0 - 0 . 0 5 3 . 8 1 r e f 0 . 6 0 0 . 0 5 p i n 1 i d e x p o s e d m e t a l p a d s h o u l d b e l e f t f l o a t i n g . 6 . 8 0 0 . 6 0 1 . 2 7 r e c o m m e n d e d p c b f o o t p r i n t 1 . 4 s i l k s c r e e n p i n 1
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 15 of 17 mechanical drawing 8 - pin dip * jedec ms - 001 refer to jedec ms - 001 for complete dimensions and notes. controlling dimensions in inches. pdip package marking scheme legend: xxxxx= part number, p=package (p=pdip green), t=temp. range (c=commercial, =industrial) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm25h20, green/rohs pdip package, rev. a, lot 0448727 , year 2011, work week 03 25h2 0 - p a0448727 ric1103 xxxx x - pt rll llll l ricyyww index area 0 . 280 max 0 . 240 min 0 . 400 max 0 . 355 min 0 . 015 min 0 . 100 bsc 0 . 005 min 0 . 022 max 0 . 014 min 0 . 195 max 0 . 115 min 0 . 210 max 0 . 300 nom 0 . 430 max 0 . 325 max 0 . 300 min
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 16 of 17 8 - pin eiaj soic all dimensions in millimeters . eiaj soic package marking scheme legend: xxxxxx= part number , p = package (g=g reen ), t=temp (blank=ind., c=c omm.) r=rev code, lllllll= lot code ric=ramtron intl corp, yy=year, ww=work week example: fm25v20, green /rohs eiaj soic package, rev a, lot 0448727, year 2010, work week 29 fm25v 20 - g a 0448727 ric 1029 pin 1 5 . 28 0 . 10 8 . 00 0 . 25 5 . 23 0 . 10 0 . 05 0 . 25 1 . 78 2 . 00 0 . 36 0 . 50 1 . 27 0 . 10 mm 0 . 51 0 . 76 0 . 19 0 . 25 0 ? - 8 ? recommended pcb footprint 9 . 30 0 . 65 1 . 27 2 . 15 5 . 00 xxxxxxx - pt r lllllll ric yyww
fm25v20 C 2mb spi f - ram rev. 3.0 august 2012 page 17 of 17 revision history revision date sum mary 1.0 6 / 15 /20 10 initial release. 1.1 8/8/2011 removed s/n options. 1.2 11/21/2011 added esd ratings. 2.0 12/20 /2011 changed to pre - production status. changed t pu and t rec spec s . 3.0 0 8 / 13 /2012 changed to production status . parameters t od, t oh, t r , t f, t hh, t hz & t lz changed to guaranteed by design. a dded pdip package. note: package s marked * are under package vendor re - qualification . ordering information part number features operating voltage operating t emp. package fm 25v20 - g device id 2.0 - 3.6v - 40c to +85 c 8 - pin green/rohs eiaj fm25v20 - dg device id 2.0 - 3.6v - 40c to +85c 8 - pin green/rohs tdfn * fm25v20 - pg device id 2.0 - 3.6v - 40c to +85c 8 - pin green/rohs pdip * fm25v20 - gtr device id 2.0 - 3.6v - 40c to +85c 8 - pin green/rohs eiaj, tape & reel fm25v20 - dgtr device id 2.0 - 3.6v - 40c to +85c 8 - pin green/rohs tdfn, tape & reel

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